This invention relates to analog-to-digital converters. It is disclosed in the context of analog-to-digital converters for use in power measuring instruments. However, it is believed to be useful in other applications as well.
There are many variations on analog-to-digital (hereinafter sometimes A/D) conversion techniques Most implementations can be placed in one of six categories. These are successive approximation, flash, voltage-to-frequency, dual slope, charge balancing, and delta-sigma.
Successive approximation converters generally employ a sample-and-hold circuit, a comparator, a digital-to-analog converter and some control logic. The input signal is first captured by the sample-and-hold circuit and then a search pattern is executed using the digital-to-analog converter and the comparator. For optimization of speed, the search pattern is usually a binomial type. The input signal is scaled to be somewhere within the range of the output of the digital-to-analog converter. In the binomial search pattern the digital-to-analog converter is set to half scale and the comparator is used to determine if the captured input signal is higher or lower than the output of the digital-to-analog converter. This eliminates half of the possible results and thus determines the most significant bit of the conversion. The digital-to-analog converter is then reset to bisect the remaining voltage range and the comparator is again used to determine in which half the input voltage resides. This determines the next most significant bit. The process is repeated until the number of bits required is achieved. A twelve-bit converter requires twelve such comparisons.
Flash converters make use of a divider ladder, multiple comparators and decode logic to perform the A/D conversion. There are as many comparators and taps on the divider ladder as there are codes in the A/D converter. An 8-bit converter requires 256 comparators and 256 taps on the divider. A 12-bit converter, if produced, would require a staggering 4096. The comparators then compare the incoming signal against their respective tap voltages. Comparators with tap voltages above the input voltage assume a first state. Those with tap voltages below the input voltage assume a second state. The outputs of all the comparators are fed into the decode logic to create the output. Because they perform all the comparisons at one time, flash converters are generally considered the fastest of these six kinds of A/D converters.
Dual slope converters are a form of integrating converter. They work by measuring charge accumulated in a capacitor. If not already a current, the input signal is converted to a current and applied to a discharged capacitor for a fixed period of time. An operational amplifier, hereinafter op-amp, -based integrator circuit is frequently used to provide an extremely low burden to the input current source. Since current multiplied by time is charge and the charging time is fixed, the charge that is placed in the capacitor is proportional to the average input current. As the charge is applied, the voltage of the capacitor ramps up. This is the first slope to which the name dual slope converter refers. Next, the second step of measuring this charge is conducted. To measure the charge accumulated, the charging process is ended, and a calibrated discharging current is applied. The time required to return the capacitor to the discharged state is measured. As the charge is removed, the voltage across the capacitor ramps back down to zero. When the capacitor voltage returns to zero, exactly the amount of charge which resulted from the input current has been removed. This is the second slope to which the dual slope name refers. Since the discharge current applied and the time it was applied are both known, the charge that was removed from the capacitor, and therefore the charge that accumulated in the capacitor resulting from the input signal, is also known. If this charge is then divided by the time required for the input current to charge it, the average input current for the measurement period is calculated.
A charge balance converter is another form of integrating converter. Charge balance converters are similar to dual slope converters, in that the input signal to a charge balance converter is a current or is converted to a current, and the charge being accumulated in a capacitor is measured. They differ primarily in how charge is measured and removed. In a charge balance converter, charge continuously accumulates in the capacitor, while being simultaneously being removed in discrete quanta. Periodically, the voltage across the capacitor is measured. If enough charge has accumulated, a packet of charge is removed. This is usually accomplished by applying a calibrated current for a specific period of time. For each sample period when a packet of charge is removed, a pulse is output by the converter. If no charge is removed during the sample period, no pulse is output. The pulses, when present, appear at periodic boundaries. The frequency of the pulses is then measured to complete the conversion.
A voltage-to-frequency converter is another form of integrating converter. Voltage-to-frequency converters are similar to dual slope and charge balance converters in that the input is a current, or is converted from a voltage to a current and the charge accumulated in the capacitor is measured. They differ from dual slope- and charge balance converters in how the charge is removed. As in charge balance converters, in voltage-to-frequency converters charge is removed in discrete quanta. Unlike charge balance converters, voltage-to-frequency converters remove the charge whenever a full quantum or packet of charge has accumulated. Thus, in voltage-to-frequency converters, charge is not removed on periodic boundaries. This causes the converter to provide an output frequency which is proportional to the applied input current. The National Semiconductor LM131 family of voltage-to-frequency converters is a good example of this type of A/D converter.
The delta-sigma converter is yet another form of integrating converter. Delta-sigma converters are a highly specialized form of the charge balance converter, but are discussed separately here. The delta-sigma converter can be considered as two components, a modulator and a digital filter. The modulator contains the converter""s integrating portion and charge removal portion. The modulator effectively functions as a very high speed, 1 bit digitizer with a very unique noise spectrum. This 1 bit digitizer samples at a frequency that is several orders of magnitude higher than the frequency band of interest. Because of its unique construction, the noise spectrum it produces is non-uniformly distributed and the bulk of the noise energy is outside of the frequency band of interest. Thus, by proper filtering much of this noise can be removed. This is one function served by the digital filter. The modulator is interesting in that it can perform the voltage-to-current conversion as an inherent part of its function, and thus, from the user""s perspective, the input to the converter is usually a voltage instead of a current. The digital filter performs two functions. It functions as a very sophisticated version of the counter in the charge balance converter, as well as a digital filter to extract a higher resolution result at a lower data rate than the 1 bit digitizer.
Traditional power measurement has principally revolved around measuring power flow in power delivery circuits. The measurements, whether they are watts, watt-hours, VoltAmpereSReactive (VARS), Q-hours, or the like, have usually been measured one at a time. Performing these measurements involves the precision multiplication of a voltage signal and a current signal. Traditionally this has been performed with analog circuitry. The most commercially successful of these circuits has been the pulse width modulator. In communications circuitry, it is often referred to as a balanced mixer or ring demodulator. In any case, the function is identical.
In a typical pulse width modulator, the first of the two signals controls a circuit which chops the polarity of the second signal in a pulse width-controlled manner, depending upon the amplitude of the first signal. The output of the circuit is a series of harmonics which are multiples of the frequencies of the two signals and a DC component which is proportional to the coincidence of the two signals. The output is low pass filtered to eliminate everything except the DC component and then converted into a digital signal.
A drawback of a pulse width modulator is that it can only produce one measurement at a time. The multiplication occurs in the modulator itself. Power consumers are now beginning to demand simultaneous measurement of multiple parameters. Power consumers are also asking for power suppliers to measure more parameters. Consumers are now asking for information on the harmonics of the power signal. They want to know such information from the fundamental out to the fiftieth harmonic for both 50 and 60 Hz systems. This means that accurate measurements must be performed all the way from 45 Hz to 3 KHz. At the fundamental frequency, customer accuracy expectations require better than 0.01% (100 PartsPerMillion) and grow only to 0.1% (1000 PPM) by the fiftieth harmonic. One good way of meeting these needs is to digitize the voltage and current waveforms and perform the mathematical operations on the digitized data stream.
Because power is being measured with extreme accuracy and wide bandwidth requirements, significant demands are imposed on the analog-to-digital converters used to digitize the voltage and current waveforms. Sampling rates must be quite high. Since accurate measurements must be made out to 3 KHz, at least at 6K samples per second must be taken. Ideally, samples should be taken at least an order of magnitude more frequently to make the anti-aliasing filter easier to implement. Lower sampling rates are possible, but this increases the difficulty of implementing an anti-aliasing filter with negligible phase shift at the frequencies of interest.
The required gain accuracy is also quite high. In order to achieve a worst-case system accuracy, the rule of thumb is that all subsystems of the instrument must typically be performing at least an order of magnitude better. This means that at 60 Hz, the A/D converter needs to have an accuracy of 0.001% (10 PPM). To achieve this level of accuracy, an A/D converter needs a minimum effective resolution of at least 17 bits (log(100,000)/log(2)=16.6≈17). Because power factors down to about 0.5 will need to be measured, an additional bit will need to-be measured to maintain the dynamic range. Thus, 18 bits will need to be measured. Because it is also expected that the A/D converter will operate with input signals at half of full scale, another bit of resolution will be required. This increases the requirement to 19 bits. Since most commercially available A/D converters perform at a much lower effective resolution than their number of bits would imply, an A/D converter resolution of from 20 to 22 bits is a realistic requirement.
Further, since two separate signals are to be multiplied together, phase accuracy or knowing exactly when in time a waveform""s sample was taken relative to the other waveform""s sample needs to be known. At 60 Hz and a power factor of 0.5 (60 degrees), an error in time between the two signals of only 153 nanoseconds (nsec) causes a 0.01% (100 PPM) error in the calculated result. When operating at 3 KHz at 0.5 power factor, a 30.6 nsec error in time between the two signals causes a 0.1% (1000 PPM) error in the calculated result. These errors consume the entire error budgets for the system. In order to comply with the order of magnitude rule for any individual component, time error needs to be controlled to within 3 nsec for 3 KHz signals and 15.3 nsec for 60 Hz signals.
The combined speed and resolution requirements almost immediately eliminate all the current, commercially available, successive approximation, flash, and dual slope A/D converters. Most remaining commercially available, high-speed, high-resolution A/D converters have been designed with audio conversion in mind. Absolutely flat frequency response between 45 Hz and 3 KHz is not uppermost among design criteria for audio A/D converters. A passband with 0.1 dB ripple is quite acceptable from an audio point of view. Unfortunately it would cause up to 11,579 PPM of error in this application. Many audio A/ID converters also have built-in filters to reject 50 and 60 Hz signals. Finally, audio A/D converters generally make no effort to synchronize channels to the nanosecond level. There is no practical requirement to do so in audio applications.
According to one aspect of the invention, a circuit for analog-to-digital (A/D) conversion of an input signal includes an integrator. The integrator includes a capacitance and an amplifier. The capacitance is coupled to an input port of the amplifier. The circuit further includes an A/D converter coupled to an output port of the amplifier, a reference source for changing the amount of charge stored in the capacitance at a known time rate, and at least one switch for alternately coupling the reference source and the input signal to the capacitance. The circuit further includes a processor for controlling an A/D conversion cycle of the A/D converter and for controlling the coupling of the input signal and the reference source to the capacitance.
Illustratively according to this aspect of the invention, the processor includes a processor for summing outputs from the A/D converter during successive cycles and dividing by the number of summed outputs to increase the resolution of the A/D converter output.
Further illustratively according to this aspect of the invention, the processor includes a processor for summing outputs from two consecutive cycles and dividing by two.
Additionally illustratively according to this aspect of the invention, the processor includes a processor for summing outputs from four consecutive cycles and dividing by four.
Illustratively according to this aspect of the invention, the amplifier includes multiple amplifiers in cascade configuration to increase the gain of the amplifier cascade.
Further illustratively according to this aspect of the invention, the multiple amplifiers include multiple video amplifiers.
Additionally illustratively according to this aspect of the invention, the processor controls the at least first switch to provide a known charge to the integrator, and controls the A/D converter to A/D convert the integrator output before and after the introduction of the charge.
Further illustratively according to this aspect of the invention, the circuit includes a time base generator coupled to the processor. The processor periodically operates the at least first switch to uncouple the input signal from the integrator periodically, to couple the reference source to the integrator periodically, and to provide a known charge to the integrator periodically. The A/D converter A/D converts the integrator output before and after the periodic introduction of the charge.
Illustratively according to this aspect of the invention, the processor determines from the A/D converted integrator output before and after the introduction of the charge the effective capacitance of the integrator and A/D converter combination.
Additionally illustratively according to this aspect of the invention, the integrator including a capacitance and an amplifier includes a first integrator including a first capacitance and a first amplifier and a second integrator including a second capacitance and a second amplifier. The first and second capacitances are so oriented in the apparatus that their temperatures remain substantially the same during operation of the apparatus. The processor determines from the A/D converted first integrator output before and after the introduction of the charge the effective capacitance of the first integrator and A/D converter combination and concludes that changes in the effective capacitance of the second integrator are comparable.
Illustratively according to this aspect of the invention, the temperature coefficient of the capacitance is known. The processor determines from the change in the effective capacitance of the capacitance and the temperature coefficient of the capacitance the temperature of the capacitance.
Further illustratively according to this aspect of the invention, the reference source includes a first reference source and a second reference source. The at least first switch includes at least a first switch for selectively uncoupling the input signal from the integrator and coupling the first reference source to the integrator and at least a second switch for selectively coupling the second reference source to the integrator. The processor controls the at least first switch to provide a first charge to the integrator, controls the A/D converter to A/D convert the integrator output after the introduction of the first charge, controls the at least second switch to remove a second charge calculated to be equal to the first charge, and controls the A/D converter to A/D convert the integrator output after the removal of the second charge to provide an offset voltage of the integrator and the A/D converter.
Additionally illustratively according to this aspect of the invention, the at least first switch selectively uncouples the input signal from the integrator and discharges the integrator. The processor controls the A/D converter to A/D convert the integrator output after the integrator is discharged, and calculates the amplifier bias current from the output of the A/D converter after the integrator has been discharged.
Further illustratively according to this aspect of the invention, the circuit includes a time base generator coupled to the processor. The processor controls the A/D converter to A/D convert the integrator output after the integrator capacitor is charged to determine leakage from the integrator capacitor.
Illustratively according to this aspect of the invention, the processor controls the at least first switch for providing a known charge to the integrator. The processor also controls the A/D converter to A/D convert the integrator output before and after the introduction of the charge. The processor includes a table of values to compensate the A/D converted integrator output by the difference between the A/D converted integrator output and the known charge.
Further illustratively according to this aspect of the invention, the processor operates the at least first switch a lesser number of times to charge the capacitance to a calculated value. The A/D converter then A/D converting a first output of the integrator. The processor then operates the at least first switch a greater number of times to charge the capacitance to the calculated value. The A/D converter then A/D converts a second output of the integrator. The processor then determines a difference between the A/D converted first output and the A/D converted second output, divides the difference between the A/D converted first output and the A/D converted second output by the difference between the greater number and the lesser number, and stores the quotient as a charge injection parameter.
Additionally illustratively according to this aspect of the invention, the processor operates the at least first switch once to charge the capacitance to the calculated value.
Illustratively according to this aspect of the invention, the greater number of times is at least one hundred times the lesser number of times.
Further illustratively according to this aspect of the invention, the reference source includes a first reference source for changing the amount of charge stored in the capacitance at a first known time rate and a second reference source for changing the amount of charge stored in the capacitance at a second known time rate. The at least a first switch selectively couples the first reference source to the integrator to charge the capacitance a first known amount and uncouples the second reference source from the integrator, and selectively uncouples the first reference source from the integrator and couples the second reference source to the integrator to charge the capacitance a second known amount. The processor compares the first and second known amounts to calibrate the second reference source to the first reference source.
Illustratively according to this aspect of the invention, the integrator is a first integrator including a first capacitance and a first amplifier. The first capacitance is coupled to an input port of the first amplifier. The A/D converter is a first A/D converter. The circuit further includes a second integrator including a second capacitance and a second amplifier. The second capacitance is coupled to an input port of the second amplifier. The circuit further includes a second A/D converter. The at least one switch selectively couples the reference source to the first integrator of to the second integrator. The processor controls the position of the at least first switch, controls a first A/D conversion cycle of the first A/D converter to produce a first A/D converter output, and controls a second A/D conversion cycle of the second A/D converter to produce a second A/D converter output.
Further illustratively according to this aspect of the invention, the input signal is an input current signal and the reference source includes a current reference source.
Additionally illustratively according to this aspect of the invention, the input signal is an input voltage signal. The circuit further includes a second amplifier and a resistance for converting the input voltage signal to an equivalent input current signal.
Illustratively according to this aspect of the invention, the reference source includes a first voltage reference source for changing the amount of charge stored in the capacitance at a first known time rate and a second voltage reference source for changing the amount of charge stored in the capacitance at a second known time rate. The at least first switch selectively couples the first voltage reference source to the integrator to charge the capacitance a first known amount and uncouples the second voltage reference source from the integrator, and uncouples the first voltage reference source from the integrator and couples the second voltage reference source to the integrator to charge the capacitance a second known amount.
Further illustratively according to this aspect of the invention, the second amplifier and resistance for converting the input voltage signal to an equivalent input current signal includes a second amplifier and first resistance for converting one of the input voltage signal, the first voltage reference source and the second voltage reference source to a first equivalent input current signal, and a third amplifier and second resistance for converting one of the input voltage signal, the first voltage reference source and the second voltage reference source to a second equivalent input current signal. The processor alternately couples said one of the input voltage signal, the first voltage reference source and the second voltage reference source through the second amplifier to produce a first A/D converter output and through the third amplifier to produce a second A/D converter output, and averages the first A/D converter output and the second A/D converter output.
Additionally illustratively according to this aspect of the invention, the first reference source has a first polarity, and the second reference source has a second and opposite polarity. Charging the capacitance a second known amount includes discharging the capacitance from the first known amount.
Illustratively according to this aspect of the invention, the at least first switch has a position in which no input signal is present. The processor stores A/D converter output when the at least first switch is in the position in which no input signal is present.
Further illustratively according to this aspect of the invention, the at least first switch includes a first switch for alternately coupling the reference source and the input signal to the second amplifier and a second switch for alternately coupling and uncoupling the second amplifier to the capacitance. The second switch is characterized by a second resistance. The circuit further includes a negative resistance device having a second resistance, the magnitude of which is substantially the magnitude of the first resistance, for coupling in circuit with the first resistance.
Further illustratively according to this aspect of the invention, the circuit includes a power supply for providing power for at least one of the integrator, the A/D converter, the reference source, the switch, and the processor. The power supply generates periodic signals during its operation. The processor synchronizes the A/D conversion cycle and the periodic signals so that the effect of the periodic signals on the A/D converter output is substantially constant.
According to another aspect of the invention, a circuit for A/D conversion of an input signal includes an integrator including an amplifier and a capacitance coupled to an input port of the amplifier. The circuit further includes an A/D converter coupled to an output port of the amplifier, a reference source for changing the amount of charge stored in the capacitance at a known time rate, and a processor for controlling an A/D conversion cycle of the A/D converter. The input signal has a first polarity, and the reference source has a second and opposite polarity. The capacitance is simultaneously charged and discharged by the input signal and the reference source prior to each A/D conversion cycle.
Further illustratively according to this aspect of the invention, the circuit includes at least one switch. The reference source includes a first reference source for changing the amount of charge stored in the capacitance at a first known time rate and a second reference source for changing the amount of charge stored in the capacitance at a second known time rate. The at least first switch selectively couples the first reference source to the integrator to change the amount of charge stored in the capacitance at the first known time rate, couples the second reference source to the integrator to change the amount of charge stored in the capacitance at the second known time rate, and couples both the first and second reference sources to the integrator to change the amount of charge stored in the capacitance at the algebraic sum of the first known time rate and the second known time rate.
Illustratively according to this aspect of the invention, the processor controls the at least one switch to couple the first reference source to the integrator, or to couple the second reference source to the integrator, or to couple both the first and second reference sources to the integrator based upon the A/D converter output during a preceding A/D conversion cycle.
Further illustratively according to this aspect of the invention, the processor adjusts the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least one preceding A/D conversion cycle and the A/D converter output during at least one succeeding A/D conversion cycle.
Additionally illustratively according to this aspect of the invention, the processor adjusts the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least the immediately preceding A/D conversion cycle and the A/D converter output during at least the immediately succeeding A/D conversion cycle.
Illustratively according to this aspect of the invention, the processor adjusts the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least the two immediately preceding A/D conversion cycles and the A/D converter output during at least the two immediately succeeding A/D conversion cycles.
According to yet another aspect of the invention, a method for analog-to-digital (A/D) conversion of an input signal includes providing an integrator including a capacitance coupled to an input port of an amplifier, coupling an A/D converter to an output port of the amplifier, changing the amount of charge stored in the capacitance at a known time rate by alternately coupling the input signal and a reference source to the capacitance through at least one switch, and controlling an A/D conversion cycle of the A/D converter and the at least one switch for controlling the coupling of the input signal and the reference source to the capacitance with a processor.
Further illustratively according to this aspect of the invention, the method includes summing outputs from the A/D converter during successive cycles and dividing by the number of summed outputs to increase the resolution of the A/D converter output.
Illustratively according to this aspect of the invention, summing outputs from the A/D converter during successive cycles and dividing by the number of summed outputs includes summing outputs from two consecutive cycles and dividing by two.
Additionally illustratively according to this aspect of the invention, summing outputs from the A/D converter during successive cycles and dividing by the number of summed outputs includes summing outputs from four consecutive readings and dividing by four.
Illustratively according to this aspect of the invention, providing an integrator including a capacitance coupled to an input port of an amplifier includes providing multiple amplifiers in cascade configuration to increase the gain of the amplifier cascade.
Further illustratively according to this aspect of the invention, providing multiple amplifiers includes providing multiple video amplifiers.
Additionally illustratively according to this aspect of the invention, providing an integrator including a capacitance coupled to an input port of an amplifier includes providing a video amplifier.
Illustratively according to this aspect of the invention, controlling the at least first switch includes controlling the at least first switch to provide a known charge to the integrator, and controlling the A/D conversion cycle includes controlling the A/D conversion cycle to A/D convert the integrator output before and after the introduction of the charge.
Further illustratively according to this aspect of the invention, the method includes periodically operating the at least first switch to uncouple the input signal from the integrator and couple the reference source to the integrator to provide a known charge to the integrator. Coupling an A/D converter to the integrator output includes A/D converting the integrator output before and after the periodic introduction of the charge.
Additionally illustratively according to this aspect of the invention, controlling an A/D conversion cycle of the A/D converter and the at least one switch for controlling the coupling of the input signal and the reference source to the capacitance with a processor includes determining from the A/D converted integrator output before and after the introduction of the charge the effective capacitance of the integrator and A/D converter combination.
Illustratively according to this aspect of the invention, providing an integrator including a capacitance coupled to an input port of an amplifier includes providing a first integrator including a first capacitance coupled to an input port of a first amplifier and providing a second integrator including a second amplifier and a second capacitance coupled to an input port of the second amplifier, the second capacitance so oriented its temperature remains substantially the same as the temperature of the first capacitance during performance of the method. Determining from the A/D converted integrator output before and after the introduction of the charge the effective capacitance of the integrator and A/D converter combination includes determining from the A/D converted first integrator output before and after the introduction of the charge the effective capacitance of the first integrator and A/D converter combination, and concluding that changes in the effective capacitance of the second integrator are comparable.
Further illustratively according to this aspect of the invention, providing an integrator including a capacitance includes providing a capacitance, the temperature coefficient of which is known. The method further includes determining from the change in the effective capacitance of the capacitance and the temperature coefficient of the capacitance the temperature of the capacitance.
Additionally illustratively according to this aspect of the invention, alternately coupling the reference source to the capacitance through at least a first switch includes alternately coupling a first reference source through at least a first switch for selectively uncoupling the input signal from the integrator and coupling the first reference source to the integrator and alternately coupling a second reference source through at least a second switch for selectively coupling the second reference source to the integrator, controlling the at least first switch for providing a first charge to the integrator, controlling the A/D converter to A/D convert the integrator output after the introduction of the first charge, controlling the at least second switch for removing a second charge calculated to be equal to the first charge, and controlling the A/D converter to A/D convert the integrator output after the removal of the second charge to provide an offset voltage of the integrator and the A/D converter.
Illustratively according to this aspect of the invention, alternately coupling the input signal and the reference source to the capacitance through at least one switch includes selectively uncoupling the input signal from the integrator and discharging the integrator. Controlling an A/D conversion cycle of the A/D converter and the at least one switch for controlling the coupling of the input signal and the reference source to the capacitance with a processor includes controlling the A/D converter to A/D convert the integrator output after the integrator is discharged and calculating the amplifier bias current from the output of the A/D converter after the integrator has been discharged.
Further illustratively according to this aspect of the invention, the method includes controlling the A/D converter to A/D convert the integrator output after the integrator capacitor is charged to determine leakage from the integrator capacitor.
Additionally illustratively according to this aspect of the invention, the method includes controlling the at least first switch to provide a known charge to the integrator, controlling the A/D converter to A/D convert the integrator output before and after the introduction of the charge, and providing a table of values to compensate the A/D converted integrator output by the difference between the A/D converted integrator output and the known charge.
Illustratively according to this aspect of the invention, the method includes operating the at least first switch a lesser number of times to charge the capacitance to a calculated value and A/D converting a first output of the integrator, operating the at least first switch a greater number of times to charge the capacitance to the calculated value and A/D converting a second output of the integrator, determining a difference between the A/D converted first output and the A/D converted second output, dividing the difference between the A/D converted first output and the A/D converted second output by the difference between the greater number and the lesser number, and storing the quotient as a charge injection parameter.
Further illustratively according to this aspect of the invention, operating the at least first switch a lesser number of times to charge the capacitance to the calculated value includes operating the at least first switch once to charge the capacitance to the calculated value.
Additionally illustratively according to this aspect of the invention, the greater number of times is at least about one hundred times the lesser number of times.
Illustratively according to this aspect of the invention, coupling a reference source to the capacitance through at least one switch includes changing the amount of charge stored in the capacitance at a first known time rate by coupling a first reference source to the capacitance and changing the amount of charge stored in the capacitance at a second known time rate by coupling a second reference source to the capacitance. The at least a first switch selectively couples the first reference source to the integrator to charge the capacitance a first known amount and uncouples the second reference source from the integrator, and uncouples the first reference source from the integrator and couples the second reference source to the integrator to charge the capacitance a second known amount. The method further includes comparing the first and second known amounts to calibrate the second reference source to the first reference source.
Further illustratively according to this aspect of the invention, coupling a first reference source to the capacitance includes coupling a first reference source having a first polarity to the capacitance. Coupling a second reference source to the capacitance includes coupling a second reference source having a second and opposite polarity to the capacitance. Charging the capacitance a second known amount includes discharging the capacitance from the first known amount.
Additionally illustratively according to this aspect of the invention, providing an integrator including a capacitance coupled to an input port of an amplifier includes providing a first integrator including a first amplifier and a first capacitance coupled to an input port of the first amplifier, and providing a second integrator including a second amplifier and a second capacitance coupled to an input port of the second amplifier. Coupling an A/D converter to an output port of the amplifier includes coupling a first A/D converter to an output port of the first amplifier, coupling a second A/D converter to an output port of the second amplifier. Alternately coupling the input signal and a reference source to the capacitance through at least one switch includes selectively coupling the reference source to the first integrator or to the second integrator. Controlling an A/D conversion cycle of the A/D converter with the processor includes controlling a first A/D conversion cycle of the first A/D converter for producing a first A/D converter output and controlling a second A/D conversion cycle of the second A/D converter for producing a second A/D converter output.
Illustratively according to this aspect of the invention, the input signal is an input current signal. Alternately coupling the input current signal and a reference source to the capacitance includes alternately coupling the input current signal and a current reference source to the capacitance.
Further illustratively according to this aspect of the invention, the input signal is an input voltage signal. The method further includes providing a second amplifier and a first resistance for converting the input voltage signal to an equivalent input current signal.
Additionally illustratively according to this aspect of the invention, alternately coupling the input signal and a reference source to the capacitance through at least one switch includes alternately coupling a first voltage reference source for changing the amount of charge stored in the capacitance at a first known time rate and a second voltage reference source for changing the amount of charge stored in the capacitance at a second known time rate. The at least first switch selectively couples the first voltage reference source to the integrator to charge the capacitance a first known amount and uncouples the second voltage reference source from the integrator, and uncouples the first voltage reference source from the integrator and couples the second voltage reference source to the integrator to charge the capacitance a second known amount.
Illustratively according to this aspect of the invention, providing a second amplifier and a first resistance for converting the input voltage signal to an equivalent input current signal includes providing a second amplifier and first resistance for converting one of the input voltage signal, the first voltage reference source and the second voltage reference source to a first equivalent input current signal, and providing a third amplifier and second resistance for converting one of the input voltage signal, the first voltage reference source and the second voltage reference source to a second equivalent input current signal. Controlling an A/D conversion cycle of the A/D converter and the at least one switch for controlling the coupling of the input signal and the reference source to the capacitance includes alternately coupling said one of the input voltage signal, the first voltage reference source and the second voltage reference source alternately through the second amplifier to produce a first A/D converter output and through the third amplifier to produce a second A/D converter output. The method further includes averaging the first A/D converter output and the second A/D converter output.
Further illustratively according to this aspect of the invention, alternately coupling a first voltage reference source for changing the amount of charge stored in the capacitance at a first known time rate and a second voltage reference source for changing the amount of charge stored in the capacitance at a second known time rate includes alternately coupling a first voltage reference source having a first polarity for changing the amount of charge stored in the capacitance at a first known time rate and a second voltage reference source having a second polarity opposite to the first polarity for changing the amount of charge stored in the capacitance at a second known time rate.
Additionally illustratively according to this aspect of the invention, alternately coupling the input signal and a reference source to the capacitance through at least one switch includes alternately coupling the input signal, a reference source and no input to the capacitance. Controlling an A/D conversion cycle of the A/D converter and the at least one switch for controlling the coupling of the input signal and the reference source to the capacitance includes controlling an A/D conversion cycle of the A/D converter and the at least one switch for controlling the coupling of the input signal, the reference source and no input to the capacitance and storing A/D converter output when the at least first switch is in the position in which no input is present.
Illustratively according to this aspect of the invention, providing at least a first switch for alternately coupling the reference source and the input signal to the second amplifier includes providing at least a second switch for alternately coupling and uncoupling the second amplifier to the capacitance. The method further includes providing a negative resistance device having a second resistance, the magnitude of which is substantially the magnitude of the first resistance, for coupling in circuit with the first resistance.
Further illustratively according to this aspect of the invention, the method includes providing a power supply for at least one of the integrator, the A/D converter, the reference source, the switch, and the processor, which power supply generates periodic signals during its operation. Controlling an A/D conversion cycle of the A/D converter includes synchronizing the A/D conversion cycle and the periodic signals so that the effect of the periodic signals on the A/D converter output is substantially constant.
According to yet another aspect of the invention, a method of analog-to-digital (A/D) conversion of an input signal having a first polarity includes providing an integrator including a capacitance coupled to an input port of an amplifier, coupling an A/D converter to an output port of the amplifier, changing the amount of charge stored in the capacitance by coupling the input signal and a reference source having a second and opposite polarity to the capacitance, and controlling an A/D conversion cycle of the A/D converter to simultaneously charge and discharge the capacitance with the input signal and the reference source prior to each A/D conversion cycle.
Illustratively according to this aspect of the invention, changing the amount of charge stored in the capacitance by coupling the input signal and a reference source having a second and opposite polarity to the capacitance includes selectively coupling a first reference source for changing the amount of charge stored in the capacitance at a first known time rate to the integrator to change the amount of charge stored in the capacitance at the first known time rate, coupling a second reference source for changing the amount of charge stored in the capacitance at a second known time rate to the integrator to change the amount of charge stored in the capacitance at the second known time rate, and coupling both the first and second reference sources to the integrator to change the amount of charge stored in the capacitance at the algebraic sum of the first known time rate and the second known time rate.
Illustratively according to this aspect of the invention, selectively coupling the first reference source or the second reference source or both the first and second reference sources to the integrator includes controlling at least one switch to couple the first reference source to the integrator, or to couple the second reference source to the integrator, or to couple both the first and second reference sources to the integrator based upon the A/D converter output during a preceding A/D conversion cycle.
Further illustratively according to this aspect of the invention, controlling an A/D conversion cycle of the A/D converter includes adjusting the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least one preceding A/D conversion cycle and the A/D converter output during at least one succeeding A/D conversion cycle.
Additionally illustratively according to this aspect of the invention, adjusting the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least one preceding A/D conversion cycle and the A/D converter output during at least one succeeding A/D conversion cycle includes adjusting the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least the immediately preceding A/D conversion cycle and the A/D converter output during at least the immediately succeeding A/D conversion cycle.
Illustratively according to this aspect of the invention, adjusting the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least one preceding A/D conversion cycle and the A/D converter output during at least one succeeding A/D conversion cycle includes adjusting the A/D converter output during an A/D conversion cycle by an amount related to the A/D converter output during at least the two immediately preceding A/D conversion cycles and the A/D converter output during at least the two immediately succeeding A/D conversion cycles.